3D integration process flow for set-top box application: description of technology and electrical results

摘要

In this paper, the technological steps specifically developed for 3D integration of a set top box demonstrator will be presented (figure 1). The integration flow is based on a 45nm node technology top chip stacked on a 130nm node technology active bottom wafer [1]. This flow needed to develop specific wafer level packaging technologies such as:rn1. Top & bottom chips interconnectionsrn2. Temporary bonding and debonding of bottom waferrn3. High aspect ratio TSV's designed into the bottom waferrn4. Backside interconnections for subsequent packaging steprn5. Top chip stacking on bottom waferrnIn this paper, the complete process flow will be presented. Then, a technical focus will be done on the most important process steps for the 3D integration. The preliminary electrical results of the demonstrator will be discussed. Finally, some prospects for 3D integration technologies and applications will be proposed.