Coverage Driven Test Generation Framework for RTL Functional Verification

摘要

Functional verification is widely recognized as the bottleneck of the hardware design cycle. The Coverage-Driven Verification approach makes coverage the core engine that drives the whole verification flow,which enables reaching high quality verification in a timely manner. In this paper,we present a coverage driven test generation methodology and a set of tools. We present a novel method for automatic generating simulation vectors from HDL descriptions based on path coverage and constraint solving. We present a novel approach to generate functional vectors based on assertions for RTL design verification. Our approach combines program-slicing based design extraction,word-level SAT and dynamic searching techniques. We also present a coverage analysis method based on VCD file,which only replaying the simulation of the control statements in the HDL description. Experimental results show the efficiency of our methodology.