Hardware Abstraction Levels and Their Impact on Synthesis of Digital Circuits

摘要

VHDl is a hardware description language for design and modeling of hardware. Using this language, hardware can be described in various abstraction levels such as behavioral, dataflow and structural. This paper presents an overview of VHDL and description of hardware at various levels of abstraction using this language. The impact of a description level in the synthesis of hardware also will be discussed. We will present an example to discuss the concepts of the language, illustrating the structural, dataflow and behavioral levels of modeling and their differences in the implementation using Mentor Graphics CAD tools.