Variability Influence on FinFET-Based On-Chip Memory Data Paths

摘要

In this paper, we focus on the the process variations problem due to their large impact on device and circuit reliability and performance. Most of the previous studies are concentrated on memories at cell level. Few studies are focused on their impact on more complex systems, as for example their influence in a complete memory data path. In our study we conclude that the impact of variations in the FinFET-based memory cell section is the largest measured, as it is usually designed with the minimum device dimensions. Moreover, we observe a significant influence of the FinFET type (pMOS) used to implement the memory cell in terms of delay and variability robustness.