Digital signal processor having an on-chip pipelined EEPROM data memory and a on-chip pipelined EEPROM program memory

摘要

A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1× and 2× architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.