A Dynamic Power Estimation Method for System on Chip Designs

摘要

Analysis of power requirements of semiconductors integrated circuits (ICs) is getting ever more critical to avoid either over-design for power rails or unreliability under high performance stress. The scenario under which power consumption and voltage drop are calculated has to cover a realistic worst case for switching activity with sufficient coverage of circuit logic. To design the power rails and the grid optimally, IC designers seek to identify worst case power estimates so that high intensity data computations can still be handled by the manufactured silicon. Due to inherent input-pattern dependency of the power estimation problem, it is impractical to exhaustively analyze all areas of a large circuit such as a system on chip (SOC) which may contain a significantly diverse circuit blocks. This paper describes a novel approach to generate stimulus for dynamic power estimation in complex SOC circuit designs containing multi-clocks and design cores in order to obtain realistic worst-case power scenarios. There exist many methods of estimating static power usage of SOCs, and therefore the paper focuses on dynamic power of circuits. In this work, an integrated and automated Computer Aided Design (CAD) environment was developed to generate a discrete collection of stimulus segments for the internal simulation engine or for further external analysis by circuit designers. Stimulus segments are internally simulated within the CAD tool as they are being created in order to monitor the circuit switching activity scenarios and to gather the circuit node switching rates averaged over a number of clock cycles which are then written into an aggregate activity file. This integrated approach creates stimulus on its own by using power data in technology library cells without requiring a user-supplied external stimuli to look for a worst case stimulus. The CAD environment allows designers to create a test bench that can be used further in analysis of internal transient switching scenarios. For SOCs containing macro cells, this paper describes a method to incorporate the boundary functionality of such cells and design cores to obtain switching scenarios for average worst-case power. Experimental results obtained in an industry environment using various designs demonstrate the validity and usefulness of this approach for IC designs.