The directed self-assembly (DSA) technology has shown its great potential in via/contact layer fabrication for sub 10-nm technology nodes. To guarantee sufficient overlay accuracy of generated vias, only a few guiding templates with simple shapes are feasible, and thus manufacturable via patterns are limited. In addition, redundant via insertion has become a necessary step in the circuit design flow to improve reliability and yield. However, routing by only considering redundant vias or DSA may either deteriorate the redundant via insertion rate or damage via manufacturability. This paper presents the first work on detailed routing that simultaneously considers guiding template feasibility and redundant via insertion. Since different wiring patterns result in various via patterns and redundant via candidates, we develop a sophisticated routing graph model to avoid generating undesired wiring patterns. A trunk assignment method and several rip-up and rerouting techniques are also proposed for better via planning and layout optimization. Experimental results show that our router can significantly improve the redundant via insertion rate compared to a state-of-the-art DSA-aware detailed router.
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