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METHOD, EMULATOR, AND STORAGE MEDIA FOR DEBUGGING LOGIC SYSTEM DESIGN
METHOD, EMULATOR, AND STORAGE MEDIA FOR DEBUGGING LOGIC SYSTEM DESIGN
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机译:用于调试逻辑系统设计的方法、模拟器和存储介质
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摘要
A method for debugging a logic system design including a target module to be debugged. The method includes receiving a first gate-level netlist associated with the logic system design and a second gate-level netlist associated with the target module that are generated based on a description of the logic system design, obtaining runtime information of an input signal of the target module by running the first gate-level netlist, and obtaining runtime information of the target module by running the second gate-level netlist based on the runtime information of the input signal of the target module.
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