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Graph processing optimization method based on multi-FPGA accelerator interconnection
Graph processing optimization method based on multi-FPGA accelerator interconnection
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机译:基于多FPGA加速器互连的图形处理优化方法
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摘要
A graph processing optimization method that addresses the problems such as the low computation-to-communication ratio in graph environments, and high communication overhead as well as load imbalance in heterogeneous environments for graph processing. The method reduces communication overhead between accelerators by optimizing graph partitioning so as to improve system scalability.
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