NEW ARRAY LAYOUT AND PROGRAM SCHEME FOR 3D CROSSPOINT MEMORY TO LOWER LATENCY AND INCREASE ARRAY SIZE

摘要

A three-dimensional memory including bit line contacts arranged in two portions, a first portion of bit line contacts coupled to the bit lines at positions proximate a first edge of the array of memory cells and a second portion of bit line contacts coupled to the bit lines at positions proximate a second edge of the array of memory cells; and word line contacts arranged in two portions, a first portion of word line contacts coupled to the word lines at positions proximate a third edge of the array of memory cells and a second portion of word line contacts coupled to the word lines at positions proximate a fourth edge of the array of memory cells.