FLASH MEMORY CONTROLLER MECHANISM CAPABLE OF GENERATING HOST-BASED CACHE INFORMATION OR FLASH-MEMORY-BASED CACHE INFORMATION TO BUILD AND OPTIMIZE BINARY TREE WITH FEWER NODES WHEN CACHE STORES DATA FROM HOST

摘要

A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.