MULTI-CHANNEL DIGITAL ISOLATOR WITH INTEGRATED PWM INTERLOCK PROTECTION

摘要

A multi-channel digital isolator includes a digital isolator (120B) and an interlock circuit (250). The isolator includes a transmitter (305) having a transmitter output, a receiver (310) having a receiver input and a receiver output, an isolation barrier (220) coupled between the transmitter output and the receiver input, and an output buffer (360 A) having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.