首页> 外国专利> Bus driver circuit with improved transition speed

Bus driver circuit with improved transition speed

机译:总线驱动电路,具有改善的过渡速度

摘要

A bus driver circuit comprising:a first and a second circuit node (CANL, CANH; BM, BP), the first circuit node (CANL; BM) being operatively coupled to a bus line (BUS) having a bus capacitance ( CBUS) between the first and second circuit nodes (CANL, CANH; BM, BP);a switching circuit (T1-T4) which is coupled to the first circuit node (CANL; BM) and is designed to apply an output voltage (VBUS) between to apply to the first and the second circuit node (CANL, CANH; BM, BP), whereby the bus capacitance (CBUS) is charged when a control signal (STX) indicates a dominant state;a discharge circuit comprising at least one resistor (Ro), wherein the discharge circuit is coupled between the first and the second circuit node (CANL, CANH; BM, BP) and is designed to allow the bus capacitance (CBUS) to be discharged via the resistor (Ro) when the control signal (STX) has a recessive show status wherein the switching circuit is further configured to provide, in addition to the discharge circuit, a temporary current path for discharging the bus capacitance (CBUS) during a transition time period from a dominant to a recessive state,wherein the switching circuit has at least one third transistor (T2). , which is connected to the first circuit node (CANL; BM) is coupled; the temporary current path is formed by the third transistor (T2), which is designed to be activated temporarily in accordance with the control signal (STX), the at least one third transistor (T2) being selected from a large number of transistor cells or groups of transistor cells (T2 ,1, T2,2, ..., T2,N, ..., T2,2N) having load current paths connected in parallel to form the load current path of the third transistor (T2) having an effective resistance;wherein the transistor cells or groups of transistor cells are adapted to be switched on or off sequentially, so that the effective resistance of the third transistor (T2) depends on the number of transistor cells, or groups of transistor cells, that are switched on.
机译:总线驱动电路包括:第一和第二电路节点(CAN1,CANH; BM,BP),第一电路节点(CANL; BM)可操作地连接到具有总线电容(CBUS)之间的总线(总线)第一和第二电路节点(CANL,CANH; BM,BP);耦合到第一电路节点(CANL; BM)的开关电路(T1-T4),并设计用于在其之间施加输出电压(VBUS)应用于第一和第二电路节点(CANL,CANH; BM,BP),由此当控制信号(STX)表示主导状态时,总线电容(CBUS)被充电;一个放电电路,包括至少一个电阻器(RO )其中,其中放电电路耦合在第一和第二电路节点(CANL,CANH; BM,BP)之间耦合,并且被设计成允许当控制信号( STX)具有隐性展示状态GT;其中,除了放电电路之外,切换电路还被配置为提供a用于在从主导到隐性状态的过渡时间段期间将总线电容(CBUS)放电的临时电流路径,其中开关电路具有至少一个第三晶体管(T2)。 ,连接到第一电路节点(CANL; BM)耦合;临时电流路径由第三晶体管(T2)形成,该第三晶体管(T2)被设计为临时根据控制信号(STX),所述至少一个第三晶体管(T2)从大量晶体管单元中选择或晶体管电池组(T2,1,T2,2,...,T2,N,...,T2,2),其具有并联连接的负载电流路径,以形成第三晶体管(T2)的负载电流路径有效电阻;其中,晶体管电池或晶体管单元的组适于顺序地接通或断开,从而第三晶体管(T2)的有效电阻取决于晶体管单元的数量,或晶体管单元的组打开。

著录项

  • 公开/公告号DE102014118156B4

    专利类型

  • 公开/公告日2022-01-20

    原文格式PDF

  • 申请/专利权人 INFINEON TECHNOLOGIES AG;

    申请/专利号DE201410118156

  • 发明设计人 DAVID ASTROM;DIETER METZNER;PETER WIDERIN;

    申请日2014-12-08

  • 分类号H04L25/08;H04L12/40;H04L12/407;H04L25/03;G06F13/40;

  • 国家 DE

  • 入库时间 2022-08-24 23:29:21

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号