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DRAM BANDWIDTH INCREASE WITHOUT PER PIN BANDWIDTH INCREASE
DRAM BANDWIDTH INCREASE WITHOUT PER PIN BANDWIDTH INCREASE
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机译:没有每个引脚带宽增加,DRAM带宽增加
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摘要
A dynamic random access memory (DRAM) includes first and second data buses, and first and second command and address (C/A) buses. The first data bus conveys a write data to the DRAM. The second data bus conveys read data from the DRAM. The first and second C/A buses are respectively associated with the first and second data buses. In one embodiment, the first data bus conveys the write data to a first bank of memory of the DRAM simultaneously as the second data bus conveys the read data from a second bank of memory of the DRAM. In another embodiment, the first data bus conveys the write data to a first rank of memory of the DRAM simultaneously as the second data bus conveys read data from a second rank of memory of the DRAM.
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