A METHOD AND APPARATUS FOR HARDWARE ACCELERATED DATA PARSING, PROCESSING AND ENRICHMENT

摘要

The invention disclosed relates a data parser/processor and enricher accelerated by making use of at least one 'hardware accelerator or a finite state automata' (100) (i.e. FPGA, CPLD, GPU, SoC, NoC, ASIC, etc.) obtaining messages from a 'message queue / topic' (204) and extracts various information from these messages/data by parsing/processing and preferably combines with the 'original message' (301) and then forwards to another 'message queue / topic' (204) in an asynchronous way. It is in the field of systems and methods for data parsing/processing and enrichment that includes at least one 'hardware accelerator / finite state automata' (100) and parametrically initiated threads for processing and enriching the retrieved message in multiple cores of processors. These result in a data parser/processor or enricher that can be scaled in both horizontally and vertically for multiple areas of applications.