The OIS circuit according to an embodiment of the present invention operates as a SPI (Serial Peripheral Interface bus) master for a single sensor, reads and stores sensor data from the single sensor, and operates as an SPI slave, while the first SPI slave a first OIS circuit that provides a control code in a second SPI slave operation mode preceding the operation mode, and provides the sensor data in the first SPI slave operation mode; and a second SPI master that operates as an SPI master for the first OIS circuit, reads and stores the control code from the first OIS circuit in a first SPI master operation mode, and follows the first SPI master operation mode a second OIS circuit for reading and storing the sensor data in the operation mode; includes
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