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Memory accessor invailidation

机译:Memory Accordor InvailItation.

摘要

There is provided a data processing apparatus that includes memory circuitry that provides a physical address space, which is logically divided into a plurality of memory segments and stores a plurality of accessors with associated validity indicators. Each of the accessors controls access to a region of the physical address space in dependence on at least its associated validity indicator. Tracking circuitry tracks which of the memory segments contain the accessors and invalidation circuitry responds to a request to invalidate an accessor by determining a set of equivalent accessors with reference to the tracking circuitry, and invalidating the accessor and the equivalent accessors by setting the associated validity indicator of each of the accessor and the equivalent accessors to indicate that the accessor and the equivalent accessors are invalid.
机译:提供了一种数据处理装置,其包括提供物理地址空间的存储器电路,其逻辑地被划分为多个存储段,并将多个附件存储有相关的有效性指示符。 每个访问者控制至少其相关的有效指示符的对物理地址空间的区域。 跟踪电路跟踪哪些存储器段包含访问器和无效电路响应于通过在跟踪电路确定一组等效的访问器来响应对访问者无效的请求,并通过设置相关的有效指示符使访问器和等效访问者无效 每个访问器和等效访问器中指示访问器和等效访问器无效。

著录项

  • 公开/公告号US11200175B2

    专利类型

  • 公开/公告日2021-12-14

    原文格式PDF

  • 申请/专利权人 ARM LIMITED;

    申请/专利号US202016825021

  • 发明设计人 MATTHIAS LOTHAR BOETTCHER;

    申请日2020-03-20

  • 分类号G06F12/0891;G06F12/1027;G06F9/30;G06F12/02;G06F12/0864;G06F12/14;

  • 国家 US

  • 入库时间 2022-08-24 22:47:51

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