Various arrangements for performing vector-matrix multiplication are provided herein. Digital input vectors comprising binary-encoded values may be converted into a plurality of analog signals using a plurality of 1-bit digital to analog converters (DACs). Using the analog vector matrix multiplier, a vector-matrix multiplication operation may be performed using a weighting matrix for each bit-order of the plurality of analog signals. For each vector-matrix multiplication operation performed, a bit-ordered representation of the output of the analog vector matrix multiplier may be stored. Bit-order weighted summation of sequentially performed vector-matrix multiplication operations may be performed.
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