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Compiler program, compilation method and information processing device to compile

机译:编译程序,编译方法和信息处理设备编译

摘要

To provide a compiler program, a compiling method, and an information processing device for compiling that add a prefetch instruction to a loop that repeats stride access and vectorize the loop.SOLUTION: An information processing device for compiling adds a prefetch instruction for storing access destination data of a stride access instruction in a cache memory after a predetermined number of repetitions of a loop in the loop; and adds a conditional statement for executing the prefetch instruction in the loop, and converts a stride access instruction, a conditional statement, and the prefetch instruction in the loop into a vector instruction, when variables are placed with a cache memory cache line size (C), an element length between stride accesses (m), an array element size (Type_Size), and a prefetch instruction prefetch address (x), if a remainder (x% C) when the prefetch address (x) is divided by the cache line size (C) is smaller than an address length between stride access addresses (S) obtained by multiplying the element length between stride accesses (m) by the one element size (Type_Size) ((x% C)
机译:要提供编译程序,编译方法和用于编译的信息处理设备,将预取指令添加到重复循环的循环和循环中的循环中。─Solution:用于编译的信息处理设备为存储访问目的地添加预取指令在循环中的循环的预定次数重复之后高速缓冲存储器中的步骤访问指令的数据;并添加一个条件语句,用于在循环中执行预取指令,并将循环中的升序访问指令,条件语句和预取指令转换为矢量指令,当放置具有高速缓存存储器缓存行大小(c ),跨度访问(m)之间的元素长度(m),阵列元素大小(type_size),以及预取指令预取地址(x),如果是剩余的(x%c),当预取地址(x)除以缓存时线尺寸(c)小于通过将步幅(m)之间的元素长度乘以一个元素大小(type_size)((x%c))来实现的跨度访问地址之间的地址长度小于地址长度。 :图11.

著录项

  • 公开/公告号JP6974722B2

    专利类型

  • 公开/公告日2021-12-01

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP20180009576

  • 发明设计人 向井 優太;

    申请日2018-01-24

  • 分类号G06F8/41;

  • 国家 JP

  • 入库时间 2022-08-24 22:33:02

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