A matrix vector multiplier having vector register files with multiport memory

摘要

A neural network processor including a vector register file (VRF) having multiport memory and associated methods are provided.Data processor n n × N matrix and data element n × 1 can include tiles to process vectors.The VRF stores n data elements in the multiport memory in response to a write instruction, between each of the P clock cycles The N data elements can be supplied to each of the P input interface circuits of the multiport memory.Each of the P output interface circuits comprises an input Lane configured to carry l data elements in parallel.Between each of the P clock cycles, the multiport memory can be configured to receive n data elements from at least one selected from the P input interface circuit.The VRF may include an output interface circuit that supplies n data elements in response to a read instruction.Diagram