首页> 外国专利> ORDERING COMPUTATIONS OF A MACHINE LEARNING NETWORK IN A MACHINE LEARNING ACCELERATOR FOR EFFICIENT MEMORY USAGE

ORDERING COMPUTATIONS OF A MACHINE LEARNING NETWORK IN A MACHINE LEARNING ACCELERATOR FOR EFFICIENT MEMORY USAGE

机译:订购机器学习网络中的机器学习网络的计算,以获得高效的内存用法

摘要

A compiler efficiently manages memory usage in the machine learning accelerator by intelligently ordering computations of a machine learning network. The compiler identifies a set of partial networks of the machine learning network representing portions of the machine learning network across multiple layers on which an output or set of outputs are dependent. Because any given output may depend on only a limited subset of intermediate outputs from the prior layers, each partial network may include only a small fraction of the intermediate outputs from each layer. Instead of implementing the MLN by computing one layer at a time, the compiler schedules instructions to sequentially implement partial networks. As each layer of a partial network is completed, the intermediate outputs can be released from memory. The described technique enables intermediate outputs to be directly streamed between processing elements of the machine learning accelerator without requiring large transfers to and from external memory.
机译:编译器通过智能排序机器学习网络的计算有效地管理机器学习加速器中的内存使用情况。编译器识别一组机器学习网络的一组部分网络,其跨多个层表示机器学习网络的部分,输出或一组输出依赖于此。因为任何给定的输出可以仅取决于来自先前层的中间输出的有限子集,所以每个部分网络可以仅包括来自每层的中间输出的一小部分。代替一次通过计算一层来实现一个层,代理程序调度指令以顺序实施部分网络。当部分网络的每层完成时,可以从存储器释放中间输出。所描述的技术使得中间输出能够在机器学习加速器的处理元件之间直接流式流,而不需要从外部存储器和来自外部存储器的大转移。

著录项

  • 公开/公告号US2021342675A1

    专利类型

  • 公开/公告日2021-11-04

    原文格式PDF

  • 申请/专利权人 SIMA TECHNOLOGIES INC.;

    申请/专利号US202016866513

  • 发明设计人 REED KOTLER;NISHIT SHAH;

    申请日2020-05-04

  • 分类号G06N3/063;G06N3/04;G06N3/08;

  • 国家 US

  • 入库时间 2022-08-24 22:04:47

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