Ethernet over a reduced number of twisted pair channels

摘要

An Ethernet transceiver is disclosed. The Ethernet transceiver includes transmit circuitry having a forward error correction (FEC) encoder to encode data into FEC frames. A modulator modulates the FEC frames into symbols. A precoder equalizes the symbols and a transmitter transmits the equalized symbols over a reduced number of channels NS with respect to a baseline number of channels N0. For a reduced data rate BS with respect to a baseline data rate B0, the FEC frames are assembled by the FEC encoder to exhibit an expanded frame time FTS that is expanded from a baseline frame time FT0 by a factor of B0/BS. The modulator generates symbols that are transmitted by the transmit circuit at a symbol rate SRS that is reduced from a baseline symbol rate SR0 by a factor of (B0*NS)/(BS*N0).