Processor equipped with wait shifter and control method using it

摘要

Problem to be solved: to provide a method for controlling instruction issuance in order to avoid conflict of register file write back by a plurality of instructions in the write back stage of the instruction pipeline.In the processor 100, the waiting time shifter 130 includes a plurality of shifter entries to shift out the shifter entries every clock cycle.Each of the shifter entries includes a write back value indicating the availability of the write port of the register file 140 to the write back operation in the associated clock cycle.The decoding unit 120 decodes the instruction and issues an instruction according to the waiting time rewrite value.The functional unit 160 is coupled to the decode unit and the register file to execute instructions issued by the decode unit, and write back to the write port of the register file.Diagram