首页>
外国专利>
Dsp cancellation of track-and-hold induced ISI in ADC-based serial links
Dsp cancellation of track-and-hold induced ISI in ADC-based serial links
展开▼
机译:DSP取消跟踪和保持诱导的ISI在ADC的串行链路中
展开▼
页面导航
摘要
著录项
相似文献
摘要
Apparatus and associated methods relate to targeted digital correction of a predetermined component of inter-symbol interference (ISI) associated with two or more ranks of cascaded track-and-hold (T/H) front-end circuits of a Time-Interleaved analog-to-digital converter (TI-ADC). In an illustrative example, for two T/H circuit ranks of size N and M, the predetermined component to be compensated may be located at (N×M)th unit interval (UI). A feed forward equalizer (FFE) and/or a decision feedback equalizer (DFE) in a digital signal processing system (DSP) may be then configured to have extra taps and corresponding expanded equalization ranges to mitigate the ISI. Thus, a deterministic ISI component at the N×Mth UI may be digitally corrected by providing equalization with N×M taps at low cost to facilitate scaling to higher bit rates.
展开▼