Branch prediction circuitry comprising a return address prediction structure and a branch target buffer structure

摘要

Branch prediction circuitry comprises: a return address prediction structure to store at least one predicted return address; and a branch target buffer (BTB) structure comprising entries each for specifying predicted branch information for a corresponding block of instructions. Within at least a subset of entries of the BTB structure, each entry specifies the predicted branch information with an encoding incapable of simultaneously indicating both: that the corresponding block of instructions is predicted to include a return branch instruction (for which the return address prediction structure is used to predict the target address); and the predicted target address for the return branch instruction. This can provide a more efficient BTB structure which requires less circuit area and power for a given level of branch prediction performance.