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Permutation of bit locations to reduce recurrence of bit error patterns in a memory device
Permutation of bit locations to reduce recurrence of bit error patterns in a memory device
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机译:比特位置的置换,以减少存储器设备中的误码模式的复发
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摘要
Embodiments described include methods, apparatuses, and systems including a permutation generator to permute locations of one or more bits (e.g., data bits and/or parity bits) in a codeword. In embodiments, the bits are to be written to a memory device based on the permuted locations to reduce a recurrence of bit error patterns associated with the bits when stored in the memory device. In some embodiments, the locations are based at least in part on a pseudorandom number, generated based at least in part on information available at a read time and a write time. In some embodiments, the pseudorandom number is based upon a memory address of the memory device, such as a 3D NAND or other memory device.
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