- FLOATING-POINT SUPPORTIVE PIPELINE FOR EMULATED SHARED MEMORY ARCHITECTURES

摘要

The present invention is a processor architecture arrangement for an emulated shared memory (ESM) architecture, wherein a plurality of functional units (402, 402b, 402c, 404, 404b, 404c) for performing arithmetic and logical operations on data and the same a plurality of multi-threaded processors, each provided with an interleaved inter-thread pipeline (400), said pipeline (400) comprising at least two operably parallel pipeline branches (414, 416) a first sub-group of the plurality of functional units (402, 402b, 402c), such as arithmetic logic units (ALUs), arranged to perform integer arithmetic, a first pipeline branch (414) wherein a second pipeline branch 416 is a second of the plurality of functional units 404, 404b, 404c, such as floating point units (FPUs), arranged to perform floating point operations; One or more functional units 404b of at least the second subgroup, comprising a non-overlapping sub-group, arranged for floating-point arithmetic, include memory access segments 412 and 412a of the pipeline 400 . operably positioned in parallel with