Hardware accelerators and methods for out-of-order processing

摘要

Hardware accelerators and methods for out-of-order processing are described. In one embodiment, a processor includes a hardware accelerator having a plurality of processing elements coupled to form a plurality of logical rows of a multidimensional processing array and a plurality of logical columns of the multidimensional processing array, wherein a processing element of the plurality of processing elements includes a switch to selectively source, from either of an output for a first dataset from an upstream processing element of the plurality of processing elements or a boundary condition value for a second dataset stored in the processing element, based on a switch control value provided to the processing element; and a core coupled to the hardware accelerator.