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Critical path failure analysis using hardware instruction injection
Critical path failure analysis using hardware instruction injection
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机译:使用硬件指令注入的关键路径故障分析
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摘要
Critical path failure analysis using hardware instruction injection may include providing, by an instruction microcontroller, to a plurality of processor cores, one or more test instruction sequences, wherein the instruction microcontroller is coupled to, for each of the plurality of processor cores: a first multiplexor providing an input to an instruction queue, and a second multiplexer receiving an input from the instruction queue and providing an output to an execution pathway; performing, by the instruction microcontroller, based on one or more test instruction sequences, one or more of a scan-in last pass (SLP) analysis or a scan-in cycle offset (SCO) analysis; and determining, based on one or more of the SLP analysis or the SCO analysis, one or more of a critical instruction sequence or a critical component path associated with the plurality of processor cores.
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