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Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature
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机译:数字逻辑电路,用于使用反转阵列时钟信号功能阻止阵列测试控制边界处的竞争违规
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摘要
Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scannable storage element has both a scannable storage element output and a set of flip-flops. A memory array is connected with the scannable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.
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