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Reduction of cross-capacitance and crosstalk between three-dimensionally packed interconnect wires

机译:减少三维填充互连线之间的交叉电容和串扰

摘要

A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.
机译:网格互连接口包括介电片;第一微凸块沿纵向轴线对齐,最接近驾驶员组,该驾驶员将连接到第一小芯片的第一网格停止;第二微凸块类似地与第一驾驶员银行最远的比对;第三微凸块类似地对准并定位到最靠近第二驱动器组,这将耦合到第二尖峰的第二目停止;第四微凸块类似地与第二驱动器组最偏移和定位,其中纵向轴线与小芯片之间的间隙正交。微凸块的组设置在切片上。第一组电线嵌入切片中以耦合第一和第二微凸块。第二组电线用第一组电线互动,并嵌入切片中以耦合第二和第三微凸块。

著录项

  • 公开/公告号US11043986B2

    专利类型

  • 公开/公告日2021-06-22

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201916383947

  • 发明设计人 EDWARD BURTON;

    申请日2019-04-15

  • 分类号H04B3/32;G06F15/173;

  • 国家 US

  • 入库时间 2024-06-14 21:41:51

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