LOW-COMPLEXITY DEEP LEARNING ACCELERATION HARDWARE DATA PROCESSING DEVICE

摘要

Provided is deep learning accelerator hardware which is designed to have a structure in which the number of times of accessing an external memory is reduced and a data request can be also predicted, so that data reusability is maximized and a peak bandwidth can be reduced. A deep learning accelerator according to an embodiment of the present invention comprises: a deep learning accelerator for calculating input data; an encoder for compressing output data of the deep learning accelerator; and a WDMA for recording the output data compressed by the encoder in an external memory, wherein the encoder selectively applies different compression schemes and compresses the output data on the basis of context of the output data. Therefore, the present invention can reduce the number of times of accessing an external large-capacity memory for the same channel/weight-specific data processing each time by a deep learning accelerator.