VLIW processor, instruction structure, and instruction execution method

摘要

A first operation unit 130 outputs, as a first operation result CR1, an output of a first comparison operation unit 122, or an AND or OR of the output and a value already held in a register 50 according to a first control signal ctrl. A second operation unit 140 outputs, as a second operation result CR2, an output of a second comparison operation unit 124, or an AND or OR of the output and a value already held in the register 50 according to a second control signal ctr2. A third operation unit 150 outputs, as an execution result, the first operation result CR1, or an AND or OR of the first operation result CR1 and the second operation result CR2 to the register 50 according to a third control signal ctr3. The register 50 newly holds and outputs the execution result from the third operation unit 150.