FAIL-SAFE PROCESSOR WITH ERROR CORRECTION IN THE DATA BYTE

摘要

The utility model relates to the field of computing. The technical result of the claimed utility model is the correction of errors in the information byte that occur in the computer processor when performing arithmetic and logical operations due to the absence or occurrence of unnecessary transfers. The technical result is achieved due to a fault-tolerant processor with error correction in the information byte containing the control node, the operational node, the operation code decoder, the clock pulse generator, the control unit, the first switch, the second switch, the third switch, the command counter, the shift counter, the address register, number register, adder register, additional register, additional code register, adder, block of logical operations and control, including block of logical addition according to mod2, block of inversion, block of logical addition, block of logical multiplication, functional diagram of correction formation when performing arithmetic operations, functional diagram forming a correction when performing an OR operation, a functional diagram of forming a correction when performing an AND operation, a functional diagram of generating a correction when performing a shift operation, a delay element, a first block of unequal elements, a second block of unequal elements, a third block of unequal elements, the first block of OR elements, the second block of OR elements, a coding block, the first block of AND elements, the second block of AND elements, an AND element. 3 Il.