首页> 外国专利> Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof

Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof

机译:用于高速数据通信系统的编码和解码架构及其相关物理层电路,发射器和接收器及其通信系统

摘要

A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops.
机译:发射机处的物理层电路包括编码链和多个触发器。包括串联耦合的编码单元的编码链被配置为编码多个符号以生成多个第一线状态。编码单元被布置为分别接收符号,并分别将符号的各个符号值转换为第一线状态。第一编码单元被配置为根据由第二编码单元提供的第二线状态转换相应符号的符号值。触发器被布置成分别根据时钟信号接收和输出第一线状态。其中一个触发器耦合在第一编码单元和第二编码单元之间。由第二编码单元提供的第二线状态通过触发器之一发送到第一编码单元。

著录项

  • 公开/公告号US11012087B2

    专利类型

  • 公开/公告日2021-05-18

    原文格式PDF

  • 申请/专利权人 M31 TECHNOLOGY CORPORATION;

    申请/专利号US201916701088

  • 发明设计人 CHING-HSIANG CHANG;YUEH-CHUAN LU;

    申请日2019-12-02

  • 分类号H03M9;H03M7;

  • 国家 US

  • 入库时间 2022-08-24 18:42:59

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