DRIVER AND SLEW-RATE-CONTROL CIRCUIT

摘要

A slew-rate-control (SLC) circuit (106) is coupled to an input (SS) for a driver circuit (104) to provide a first binary value (high or low) when the SLC circuit (106) is powered on and to control a slew rate when a pass element (MP1) controlled by the driver circuit (104) is enabled. The SLC circuit (106) includes a capacitor node (PN4) for coupling to a first terminal of an external capacitor (Css), the capacitor node (PN4) being coupled to the input (SS). The SLC circuit (106) also includes a SLC element (CS1) coupled between the input (SS) and a first source of voltage to define the slew rate and a reset FET (MP4) coupled between the input (SS) and a second source of voltage. The reset FET's (MP4) gate is controlled by an over-current- protection signal (OCPB) that changes binary value when a short is detected. The reset FET`s (MP4) is coupled to return the input (SS) to the first binary value responsive to detection of a short