LOW-EMI NORMALLY-ON SIC JFET DRIVING CIRCUIT

摘要

Provided in the present invention is a low-EMI normally-on SiC JFET driving circuit, comprising a drive current regulating circuit, a drive voltage clamping module, a drive power transistor Q2, a drive voltage turn-off power transistor Q3, and an inverter INV1; a drain of the drive power transistor Q2 is connected to a source of a normally-on SiC JFET power transistor Q1; a source of the drive power transistor Q2 is connected to a gate of the SiC JFET power transistor Q1 and is grounded; a gate of the drive power transistor Q2 is connected to a drive voltage vDrv; the drive current regulating circuit 110 is connected to a switch signal In; the current output end of the drive current regulating circuit 110 is connected to the gate of the drive power transistor Q2; the drive voltage clamping module 140 is connected to the gate of the drive power transistor Q2; the input end of the inverter INV1 is connected to the switch signal In, the output end is connected to a gate of the drive voltage turn-off power transistor Q3, a source of Q3 is grounded, and a drain is connected to the gate of the drive power transistor Q2. The present invention achieves a low power consumption, low-EMI normally-on SiC JFET driving circuit.