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System, method, and computer program product for sequential equivalence checking in formal verification
System, method, and computer program product for sequential equivalence checking in formal verification
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机译:用于顺序等效检查的系统,方法和计算机程序产品在正式验证中检查
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摘要
The present disclosure relates to a computer-implemented method for use in a formal verification of an electronic design. Embodiments may include receiving a reference model including a software specification, an implementation model at a register transfer level, and a property that analyzes equivalence between the reference model and the implementation model. The method may further include generating one or more case split hints based upon the reference model, that may be used to decompose the design state space into smaller partitions and performing an abstraction operation on a portion of design logic associated with one or more partitions in order to eliminate design elements that are irrelevant to a particular property. Embodiments may also include performing model checking on the abstract models to determine their accuracy.
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