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Video processing system using ring buffer and racing-mode ring buffer access control scheme

机译:视频处理系统使用环形缓冲器和赛车模式环形缓冲器访问控制方案

摘要

A video processing system includes a storage device, a receiving circuit, an audio/video demultiplexing circuit, a video decoder, and a display engine. The storage device includes a data buffer, a bitstream buffer, and a display buffer. An output of the receiving circuit is written into the data buffer. An input of the audio/video demultiplexing circuit is read from the data buffer, and an output of the audio/video demultiplexing circuit is written into the bitstream buffer. An input of the video decoder is read from the bitstream buffer, and an output of the video decoder is written into the display buffer. An input of the display engine is read from the display buffer. Each of the data buffer, the bitstream buffer, and the display buffer is a ring buffer.
机译:视频处理系统包括存储设备,接收电路,音频/视频解复用电路,视频解码器和显示引擎。存储设备包括数据缓冲器,比特流缓冲器和显示缓冲器。接收电路的输出被写入数据缓冲区。从数据缓冲器读取音频/视频解复用电路的输入,音频/视频解复用电路的输出被写入比特流缓冲区。从比特流缓冲器读取视频解码器的输入,并且将视频解码器的输出写入显示缓冲器中。从显示缓冲区读取显示引擎的输入。每个数据缓冲区,比特流缓冲区和显示缓冲区是环形缓冲区。

著录项

  • 公开/公告号US10984832B2

    专利类型

  • 公开/公告日2021-04-20

    原文格式PDF

  • 申请/专利权人 MEDIATEK INC.;

    申请/专利号US202016734384

  • 申请日2020-01-05

  • 分类号G11B20/10;H04N19/423;H04N21/44;H04N21/434;H04N21/435;H04N21/4363;G09G5/393;

  • 国家 US

  • 入库时间 2022-08-24 18:17:03

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