Optimization of multi-stage hierarchical networks for practical routing applications

摘要

Significantly optimized multi-stage networks, useful in wide target applications, with VLSI layouts using only horizontal and vertical hop wires to route large scale computational blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of partial multi-stage hierarchical networks are presented. The optimized multi-stage networks comprising partial multi-stage hierarchical networks employ one or more rings of stages of switches with inlet and outlet links of computational blocks connecting to rings from either left-hand side, or from right-hand side, or from both left-hand side and right-hand side and employ hop wires from outlet links of switches of a first stage of a first ring of a first partial multi-stage hierarchical network are connected to either inlet links of switches of the first or a second stage of the first or a second ring of the first or a second partial multi-stage hierarchical network.