首页> 外国专利> APPARATUS FOR PERFORMING DEINTERLEAVING OF A BINARY DATA STREAM AND DVB-T2 RECEIVER

APPARATUS FOR PERFORMING DEINTERLEAVING OF A BINARY DATA STREAM AND DVB-T2 RECEIVER

机译:用于执行二进制数据流和DVB-T2接收器的解交织的装置

摘要

The disclosure provides an apparatus for performing deinterleaving of a binary data stream and a DVB-T2 receiver, the apparatus comprising a mapping device and a semiconductor memory, the apparatus comprising a mapping device and a semiconductor memory; said mapping device comprising: an input interface arranged to receive said binary data stream and an output interface arranged to output a deinterleaved instance of said binary data stream; a row mapper, operatively connected to said input interface and said semiconductor memory, said row mapper being configured to group data received through said binary data stream into "write" commands for said semiconductor memory; and a row deinterleaver, operatively connected to said semiconductor memory and said output interface, said row deinterleaver being configured to present deinterleaved data, retrieved from said semiconductor memory by means of "read" commands, to said output interface; wherein said semiconductor memory is an SDRAM memory; and wherein each of said "write" commands is an SDRAM write command for at least part of an SDRAM row, said SDRAM write commands being calculated such that said deinterleaved data can be written to and read out in SDRAM burst mode. By providing a row mapper that acts on the received data stream prior to its storage in the external memory, a data ordering can be achieved that permits the retrieval of deinterleaved data at a reduced bandwidth, in particular by using a burst-read operation on an SDRAM memory.
机译:本公开提供了一种用于执行二进制数据流和DVB-T2接收器的解交织的装置,该装置包括映射设备和半导体存储器,该装置包括映射设备和半导体存储器;所述映射设备包括:输入接口,被布置为接收所述二进制数据流和设置为输出所述二进制数据流的解交织实例的输出接口;可操作地连接到所述输入接口和所述半导体存储器的行映射器,所述行映射器被配置为将通过所述二进制数据流接收的数据分组为所述半导体存储器的“写入”命令;并且可操作地连接到所述半导体存储器和所述输出接口的行解交织器,所述行解交织器被配置为借助于“读取”命令从所述半导体存储器检索到所述输出接口的排解交织器;其中所述半导体存储器是一个SDRAM记忆;并且,每个所述“写入”命令是用于SDRAM行的至少一部分的SDRAM写命令,所以正在计算SDRAM写命令,使得可以在SDRAM突发模式下写入并读出所述解交织数据。通过提供在外部存储器中的存储器之前在所接收的数据流上作用的行映射器,可以实现数据排序,以允许在降低的带宽处检索去交织数据,特别是通过使用突发读取操作SDRAM记忆。

著录项

  • 公开/公告号EP3586484B1

    专利类型

  • 公开/公告日2021-04-07

    原文格式PDF

  • 申请/专利权人

    申请/专利号EP20170897972

  • 申请日2017-02-27

  • 分类号H04L27/26;G11C7/02;G11C7/10;G11C8/04;G11C11/4076;G11C11/408;H03M13/25;H03M13/27;H03M13;H04L1;G11C11/4096;

  • 国家 EP

  • 入库时间 2022-08-24 18:05:47

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