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Low-power, low-latency time-to-digital-converter-based serial link
Low-power, low-latency time-to-digital-converter-based serial link
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机译:基于低功耗的低延迟时间到数字转换器的串行链路
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摘要
A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.
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