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Methods to design and uniformly co-fabricate small vias and large cavities through a substrate

机译:通过基板设计和均匀地共造成小通孔和大腔的方法

摘要

A method of forming concurrently openings in a substrate or wafer or a portion of substrate or wafer openings therein at least one of the openings has a relatively high aspect ratio and another one of the openings has a relatively low aspect ratio, the method comprising: bonding the substrate or wafer or a portion of substrate or wafer to a carrier substrate; forming a ring trench in the substrate or wafer or in a portion of the substrate or wafer, the ring trench having an outer perimeter that corresponds an outer perimeter of the another one of the openings having said relatively low aspect ratio and having an inner perimeter spaced from the outer perimeter by a predetermined distance; forming an opening in said substrate or wafer or in a portion of substrate or wafer having said high aspect ratio concurrently with the forming of the ring trench; and separating the substrate or wafer or in a portion of the substrate or wafer from the carrier substrate.
机译:在基板或晶片中形成同时开口的方法或其中的基板或晶片开口的一部分具有相对高的纵横比,并且另一个开口具有相对低的纵横比,该方法包括:粘合基板或晶片或基板或晶片到载体基板的一部分;在基板或晶片中形成环沟槽或在基板或晶片的一部分中,环沟槽具有外周边,其对应于具有所述相对低纵横比的另一个开口的外周边并且具有间隔的内周边从外周边通过预定距离;在所述基板或晶片中形成开口或在基板或晶片的一部分中,在形成环沟槽的同时具有所述高纵横比;并将基板或晶片分离在载体基板的基板或晶片的一部分中。

著录项

  • 公开/公告号US10957537B2

    专利类型

  • 公开/公告日2021-03-23

    原文格式PDF

  • 申请/专利权人 HRL LABORATORIES LLC;

    申请/专利号US201916557811

  • 发明设计人 FLORIAN G. HERRAULT;

    申请日2019-08-30

  • 分类号H01L21/04;H01L21/683;H01L21/308;H01L21/3065;H01L23/498;

  • 国家 US

  • 入库时间 2022-08-24 17:50:28

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