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Circuit with one of a ferromagnetic resonant change in current route which is supplied with output circuit for generating of the complement of binary signals
Circuit with one of a ferromagnetic resonant change in current route which is supplied with output circuit for generating of the complement of binary signals
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机译:具有电流路径中铁磁谐振变化之一的电路,配有输出电路,用于生成二进制信号的补码
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783,041. Ferro-resonant circuits. NATIONAL CASH REGISTER CO. Nov. 16, 1955 [Dec. 14, 1954], No. 32742/55. Class 40 (4). In a non-linear circuit controlled by a twolevel D.C. signal 9, the capacitive element C1 of series ferro-resonant circuit L1, Cl which is energized by an A.C. supply 1 is shunted by a parallel ferro-resonant circuit L2, C2 and a condenser C3, the inductors L1, L2 being saturable. An application to signal invention is described with reference to Fig. 1. In the case of a lowlevel D.C. signal in winding 4 of inductor L2, the parallel ferro-resonant circuit L2, C2 is in resonance and the high impedance of the shunt circuit establishes a highly conductive state in the series ferro-resonant circuit L1, C1. A high output potential is thus obtained at terminal 6 and is available on an output lead 8 after rectification and smoothing by components 3 and RSP1/SP, C4 respectively. Saturation of L2 by a highlevel D.C. signal disables the parallel resonance condition of L2, C2, and it is arranged so that consequential series resonance of L2 and C3 takes place. Due to the reduced impedance condition of the shunt circuit, the ferroresonant circuit L1, C1 passes into an offresonance low conductive state and a low output potential is obtained from terminal 6. Clamping diodes D1, D2 may be used to restrict the output voltage between the limits e1 and e2. The arrangement may be applied to comparison of two-level potentials at terminals 10, 11, Fig. 3, which act in opposed windings 12, 13 on inductor L2. In this arrangement a high output potential at terminal 6 is obtained only if the potentials at 10 and 11 have the same high or low value. A suggested application is the indication of errors between binary signals produced by two identical circuits which are simultaneously computing the same problem.
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