首页> 外国专利> schaltungsanordnung to implement each one of several eingangsleitungen at any time or cycle times incoming signals in a given sequence in a clocked switching signals successively occurring

schaltungsanordnung to implement each one of several eingangsleitungen at any time or cycle times incoming signals in a given sequence in a clocked switching signals successively occurring

机译:schaltungsanordnung可以在任何时间或周期时间以给定序列的输入信号连续发生的时钟切换信号中实现多个信号交换中的每一个

摘要

The logic system is for storing binary data which arrives on many parallel lines a synchronously. To attain high speed, the arrival of any data on any line produces a clock pulse which gates the data into a flip flop, then being on such flip flop corresponding to each input line. During this gating - typically several nanoseconds - other data may arrive and depending on the timing could be incorrectly stored in its corresponding flip flop. In order to avoid this a system of gates is incorporated which essentially makes a decision at appropriate moments to gate information, and this information is suitably gated itself in a hierarchial chain to prevent ambiguous inputs to the flip flops. In the case of large numbers of lines, the whole unit may be divided into sections, which are again arranged in a hierarchical structure. In each section the above chain system is effected. The result of this arrangement is that maximum speed is attained without corruption of data.
机译:逻辑系统用于存储二进制数据,该数据同步到达许多平行线上。为了达到高速,任何数据到达任何一条线上都会产生一个时钟脉冲,该时钟脉冲将数据选通到一个触发器中,然后在对应于每个输入线的这种触发器上。在此选通过程中(通常为几纳秒),其他数据可能会到达,并且根据时序可能会错误地存储在其相应的触发器中。为了避免这种情况,引入了门系统,该门系统实质上在适当的时刻做出决定以对信息进行门控,并且该信息本身在层次链中被适当地门控,以防止触发器的输入不明确。在大量的行的情况下,可以将整个单元划分为多个部分,这些部分又以分层结构排列。在每个部分中,都实现了上述链式系统。这种安排的结果是在不破坏数据的情况下达到了最大速度。

著录项

  • 公开/公告号DE000001962297A

    专利类型

  • 公开/公告日1971-07-08

    原文格式PDF

  • 申请/专利权人 LICENTIA GMBH;

    申请/专利号DE1962297A

  • 发明设计人 STANKE PETER;

    申请日1969-12-12

  • 分类号H03K17/00;

  • 国家 DE

  • 入库时间 2022-08-23 09:33:18

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