TWO{40 S COMPLEMENT NEGATIVE NUMBER MULTIPLYING CIRCUIT

• 1. 一种带负数运算的乘法计算尺 [P] . 中国专利： CN1039169C . 1998.07.15
• 2. 多字乘法－累加电路和蒙哥马利模乘法－累加电路 [P] . 中国专利： CN100504758C . 2009.06.24
• 3. BINARY TWO{40 S COMPLEMENT MULTIPLIER PROCESSING TWO MULTIPLIER BITS PER CYCLE [P] . 日本专利： JPS5615007B1 . 1981-04-08

  机译： 每周期二进二{40 S的补数乘法器处理两个乘法器位

• 4. BINARY TWO{40 S COMPLEMENT MULTIPLIER PROCESSING TWO MULTIPLIER BITS PER CYCLE [P] . 法国专利： FR2135570B1 . 1973-07-13

  机译： 每周期二进位两个{40 S的补数乘法器处理两个乘法器位

• 5. BINARY TWO{40 S COMPLEMENT MULTIPLIER PROCESSING TWO MULTIPLIER BITS PER CYCLE [P] . 美国专利： US3730425A . 1973-05-01

  机译： 每周期二进位两个{40 S的补数乘法器处理两个乘法器位

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