In a data transmission system capable of accepting an asynchronous data input and generating an FSK line signal in response to the asynchronous input, a logic processor accepts as one input the asynchronous data signal or binary facsimile signal, as a second input a frequency that is N times the frequency difference between the two frequencies which represent the two binary states, i.e., mark or space, and as a third input a frequency that is N times the frequency which represents the lower of the two frequencies representing the two binary states. The signals are combined in digital logic circuits to satisfy the logic relation D = AB(+)C where the plus indicates here Exclusive-OR addition. This results in a square wave output D that provides one of three possible output frequencies. Next the modulated wave is divided down in a binary counter to place the wave in the desired portion of the frequency band. This process suppresses substantially the third output frequency which is not desired, leaving only the two frequencies representing two binary states. Thus the two principal frequencies of the FSK signal are obtained at the output of the frequency divider, and the FSK signal has substantially continuous phase.
展开▼
