Frequency multiplying circuit - has multiplication factor which can be freely chosen

摘要

A timing frequency is applied through a stepping down device to a counting input of a forward counter, whose reading can be transmitted by each input pulse to a register, and erased. The counter reading can be repeatedly counted by the timing frequency. The stepping down device division ratio is equal to the input frequency multiplication factor. The frequency to be multiplied is applied to an input gate between the forward counter and the register. A D-flip-flop operating synchronously with the timing frequency is connected to the counter resetting input.