A MICRO PROGRAM DATA PROCESSOR HAVING PARALLEL INSTRUCTION FLOW STREAMS FOR PLURAL LEVELS OF SUB-INSTRUCTION SETS

摘要

p1426749 Microprogrammed data processor BURROUGHS CORP 5 June 1973 26717/73 Heading G4A Each micro-instruction comprises one or more syllables and includes at least an operator syllable which is used to access a corresponding control instruction in a control memory (e.g. read-only store), and the fetch of each control instruction occurs concurrently with the fetch of the microinstruction syllable which follows next after the corresponding operator syllable. As described, for each microinstruction, there is overlap between incrementation of a micromemory address register and accessing of the microinstruction memory so that a microinstruction is addressed while the address of the next microinstruction is being generated; between addressing of the microinstruction memory and fetching the preceding microinstruction from memory; and between fetching a microinstruction and fetching a control instruction for the previous microinstruction. Micro-instructions have a variable number of syllables, the first containing an operator which is used to address the control memory, and each control word defines the combination of general purpose registers to be used with an arithmetic and logic unit and the function to be performed. Overlap between microinstruction fetch and execution employs a push down stack for microinstruction addresses, and timing of a microinstruction fetch operation is dependent on the current machine state and the type of the current and next microinstructions. The processor is identical to that described in Specification 1,426,748./p[GB1426749A]