Logic networks for binary arithmetic functions - are between two registers under clock control with logic units containing mainly NAND and AND gates

摘要

A number of simple logic networks are for performing basic arithmetic functions in a typical data processor environment, in which the output of a register is operated upon and input to another registers when a clock pulse occurs. The receiving register is constructed of so called J-K flip flops, the state of which is set at a clock pulse according to the state of the inputs before and during that pulse. Logic networks comprising NAND and AND gates, are described to perform the functions of logical equivalence, non equivalence, conjunction and disjunction. These are illustrated by reference to one bit from a typical register output array.